Research On The Modeling Of On-chip Power Combiner And Its Applications For Cmos Radio-frequency Amplifier

As the rapid development of wireless mobile communication techniques, the communication data rate is higher and higher, such as the consumer data rate of the fifth-generation(5G) mobile communication, still under research, can exceed more than 1Gbps. However, compared with data rate, the improvement of communication distance isn't too much prominent. The communication distance of mobile terminals is mainly dependent on the receiver's sensitivity and transmitter's output power of wireless transceivers. Transmitted output signal is amplified by power amplifier(PA), resulting in the importance of PA design to communication distance. Furthermore, the more exiguous frequency resources lead to higher operating frequency of wireless transceiver and greater complexity of PA's design, simultaneously. For example, the next generation high-speed wireless local area network(WLAN), 802.11 ad or WiGig, adopts 60 GHz millimeter wave(mm-wave) frequency band and has been universally applied in many terminals, but the difficulty of enhancing the output power of 60 GHz PA limits the communication distance to about 1~2 meters.Monolithic transceivers including digital, analog, RF and etc. are usually fabricated using complementary metal oxide semiconductor(CMOS) process. However, the drawbacks of CMOS process, such as substrate loss and low breakdown voltage increase the design difficulty of CMOS PA. On-chip power combiner used in CMOS PA can resolve the above mentioned problems to combine the multiple PAs' output signals, which can reduce the voltage swing that each PA needs to tolerate, avoiding breaking the MOSFET down. CMOS PA adopting power combiner can output high power signal, such as AX502, a fully integrated CMOS PA using power combiner to reach 35 d Bm output power, first launched by Axiom Microdevices in 2006,.Though power combiner is widely applied in CMOS PA to output high power, the modeling of power combiner is still lack of adequate research, leading to the design complexity of on-chip power combiner. This dissertation based on the CMOS on-chip components including inductor, transformer and etc. presents the corresponding equivalent lumped circuit model of on-chip components. According to the analysis and comparison of different on-chip power combiner models, the specifications of power combiner are detailedly discussed in this research. Finally, the proposed circuit model of power combiner is verified by numerical designs and simulations, with high accuracy during GHz and mm-wave frequency bands. The model is applied in two CMOS PAs design. Detailed contents presented in this dissertation are categorized as following:Firstly, the characteristics of CMOS process are analyzed, especially the effects of metal layers and conductive substrate on on-chip components. The lumped circuit modeling and parameter extraction of on-chip inductor are thoroughly researched, with the discussion of the skin and proximity effects. Two kinds of classical circuit models of inductor are analyzed, compared, and verified through electromagnetic(EM) simulations and tapeouted silicon wafer. An example using the proposed inductor and its corresponding circuit model is also proposed: a low phase noise wideband voltage-controlled oscillator(VCO). Furthermore, the modeling of on-chip transformer is also presented and proved through measured data of tapeouted transformers with different turn ratio.Moreover, the basic theory of on-chip power combiner is analyzed with the comparisons of different models. The effects including resistive loss, coupling factor and etc. on power combiner are discussed and simulated. Full circuit model of on-chip power combiner is presented with the calculated equations related the model parameters to power combiner's specifications. Finally, the proposed model can be applied to GHz and mm-wave frequency ranges, which is proven by a mass of power combiners with different layout architectures.Furthermore, a 2.45 GHz CMOS PA based on power combiner to combine three sub-PAs' output signals is presented. Adaptive bias and diode linearization are simultaneously used to improve the PA's performances. The chip is fabricated using TSMC 0.18?m 1P6 M RFCMOS technology, meeting IEEE 802.11b/g WLAN requirements, according to the measurement results.Finally, a novel on-chip power combiner is proposed and extensively analyzed. The performance of this combiner is constant with the variations of its size and fabrication process, which can be used for different design aspects. This combiner is used in the design of a 1.9GHz CMOS PA, in which four sub-PAs are fed into the combiner. Transconductance compensation and the second harmonic termination are simultaneously used to improve the PA's linearity. The PA is simulated using TSMC 0.18?m 1P6 M RFCMOS spice model, meeting 3GPP WCDMA Band I requirements.