60 Four Floating-point Multiply-adder Design And Implementation

The work in this thesis is part of National 05' project entitled "Application Specified high performance microprocessor".There are five parts in PowerPc603e?microprocessor: Integer Execution Unit, Floating Point Unit(FPU), Instruction(Data) Cache, Bus Interface Unit and Memory Manage Unit. The instructions are executed with pipeline way. This paper studies FPU's algorithm, data-path, control-path, and implements the integration of the PowerPc603e system. This thesis mainly discusses the design and implementation of the floating point unit in the embedded PowerPc603e microrpocessor.The research work of this thesis mainly includes: Select and verify some algorithm of PowerPc603e's FPU. Design and implemention of the data-path of FPU, with emphasis in design a 64bit multiply-add unit. Which includes the design of mantissa and exponent. To the mantissa, there are six parts: part products generate and select unit, Wallace compress unit, 161bit right shifter, 161bit adder, 161bit leading zero detector and 161bit left shifter. To the exponent, there are three parts: exponent generate unit, exponent select unit, exponent adjust unit. Function simulation in three ways. Coding optimization for improving the speed of FPU. Timing simulation for verifing the setup/hold time.PowerPc603e is a complex microporcessor system. This thesis has contributed a lot to the designing of embedded microprocessor with full copyrights. The design of PowerPC603e system provided an optional method for urgent needed microprocess in aviation projects.