Research And Design Of A RISC Microprocessor

With the development of electronic technology and computer science, today's electronic system design is no longer carried out in the PCB board, using a variety of common IC. System on a chip technology, with FPGA or ASIC as its physical carrier, has become the focus of integrated circuit technique research in the 21st century. Meanwhile, the design and manufacture of microprocessor is a new and developing high technology in the current period of our country. From the RTL-level hardware description, functional simulation, synthesis optimization, layout and routing, to the post simulation and verification, this paper successfully completed the front-end design and implementation for an 8-bit RISC microprocessor.Firstly, the paper defines the overall architecture of the microprocessor and the instruction function, based on the deep study of the structure and instruction set of microprocessor. In practical design, the top-down method is used to divide the whole system into multiple modules, and this method reduces the complexity of the design to facilitate early detection of errors. And then Verilog HDL language is used for digital logic design and simulations, starting from the lowest level of the system and the interconnections of various modules from the same level constitute the hardware structure of that level. Controller, as the key module of the system, is implemented by the application of the finite state machine, And through analysis and comparison, the state encoding adopted the one-hot coding mode. At last, the function of the whole system, composed of modules of all levels, is tested and verified successfully.Secondly, the HDL codes are mapped into the specific FPGA chip by using the synthesis tool of Synplify Pro, and generate gate-level circuit netlist which meets time and size constraints after repeatedly modifying the code and constraints. Meanwhile, the problem of code synthesis is also analyzed and summarized. The FPGA chip selected in this article is EP1S10F780C6 which belongs to Altera's Stratix family.Finally,for the purpose of layout and routing, the gate-level netlist obtained in the synthesis period is send to the special EDA tool of Quartus II developed by Altera. In order to verify the design, the files generated after layout and routing, which contain the information of actual gate-level circuit, delay and driving capacity, are send to the simulator of ModelSim, and the simulation results show that the system can achieve the desired function of instructions effectively and stably. This article does not involve the back-end design of downloading to the FPGA board, but it has successfully completed the front-end design of microprocessor by using SoC technology.