Design And Research Of CPU Core Based On PIC12F683

With integrated circuit design level improved steadily, IC design has entered the system-level chip design era. The design methodology which based on IP core reuse technique can greatly improve the SOC development efficiency and reduce the design cost, thus it gradually becomes a mainstream design methodology.The research project takes the embedded IP core design technology which is one of the key techniques for the SOC design as the analysis starting-point, with the design of the 8 bits embedded microcontroller as the goal, to do the research and practice of the IP core technique.The research project is to design a RISC-CPU soft core based on PIC microcontroller, the design of RISC-CPU soft core is using the Harvard dual-bus architecture which is convenient for the realization of instruction pipeline.Through the analysis of the PIC12F683 structure, the CPU core was divided to program counter, stack, instruction register, instruction decoder, arithmetic logical unit, RAM, WDT and prescaler etc. The all blocks that we mentioned were designed using full custom design methodology which could use optimized architecture to save system resources, especially for ALU, a novel full adder using majority gate was proposed. The design of each block included function analysis, circuit realization using RTL code and the function simulation.For the purpose of improving the system operation speed, in the research project we used four stage pipeline to realize the microcontroller operation instead of two stage pipeline of PIC MCU.The instruction set of the designed CPU core was compatible with the one of another PIC MCU. The purpose of using this design method was not only to reduce the development time of the instruction set time but also to reduce the entire design time since we could use the assembler of the PIC MCU instead of developing a new assembler for the instruction set.We used advanced EDA tools to do the function simulation and synthesis to the design. The function simulation verified the functionality of the design, the synthesis optimized the design according to some related constraints. In the project, the SMIC 0.35um library was used to synthesize the RTL code of the design, the description of the RTL was realized by verilog HDL. The result of the simulation shows that the CPU operated the instructions correctly using four stage pipeline and thus indicating that we have reached the design target.