Built-in self-test solutions for high and low frequency analog/mixed-signal circuits

The scaling and integration trend in the IC world merges many blocks into a single system-on-chip (SoC) or system-in-package (SiP) concepts. Although these concepts increase the performance and minimize the area overhead, their testing on ATE is not fully accomplished due to limited pin count and high-speed requirements. Only 20-30% of area in these chips is analog/mixed-signal (AMS), but they incur the 70-80% of the test effort. In this context, built-in self-test (BIST) solutions are essential for AMS blocks.;In this work, two widely utilized blocks, low-dropout regulators (LDO) and phase-locked loops (PLL), are taken under the scope for BIST applicability since they are indispensable SoC components for generation of low noise, stable power and clock signals. Moreover, they operate at low & high frequency ends of the AMS domain.;LDO steady state current is a critical parameter for their lifetime and overall power dissipation. In this work, an on-chip steady-state current test is realized using IDDQ testing concept via built-in current sensors (BICS) in a BIST environment which minimizes ATE dependency and associated test time (> 10x). In order to increase PLL reliability, IDDQ BIST mechanism via programmable BICS is utilized on charge-pumps and 97% fault coverage is achieved. Moreover, loop parameter characterization BISTs are realized for PLLs due to their key role in PLL performance control. The characterization is accomplished by utilizing two separate BIST methodologies, i.e. current and gain extraction BISTs.;The current BIST is realized with two approaches, i.e. ratio based and architecture independent IDDQ BISTs. The former is designed to check vital PLL design parameters with respect to predefined boundaries. The latter is an on-chip current measurement tool providing a digital representation for circuit-under test current. Moreover, a self-correction mechanism is also integrated. On the other hand, the gain extraction BIST is implemented to fully control loop parameters. Two approaches, i.e. non-intrusive and intrusive are investigated. Non-intrusive method is observed to be impractical for the PLL under test. Therefore, an intrusive method with minimum degradation (3.25%) and highest accuracy (3.1%) is realized.