The Research On Low-energy Test For SoC And BIST Which Based On The State Seeds

In the mass, testing IC has two big problems: the test time is overlong and test energy is overhigh. With the IC's architecture becoming more and more complicated, testing them becomes more and more difficult. Especially for SoC, although the SoC design style allows reuse previous designs and will lead therefore to chortor time-to-market and reduced cost, on the other hand, test SoC is big challege. So how to test IC efficiently becomes more and more important.At the target of minimize the test time and the test energy,The paper presents a new low-power BIST scheme first, then on the basis of the low-power BIST scheme, the paper proposes an new test method for the test of core-based systems. The main idea of the solution is that The cores in the systems are divided into several groups,the cores in the same group share a low-power BIST that consists of a LFSR and a mapping logic, and they are tested in sequence, the LFSR and the mapping logic is used to generating the desired vectors, and the cores not in the same group are tested concurrently, the target is to minimize the test time under the power constraint. The new test architecture has some characteristics: first, it does not use external ATE, it does not rely on memory-on-chip,neither; Second,some cores share a BIST, so it decrease the hardware overheads; third,it only generating desired vectors,so itsaves lots of test time and test energy. Experimental results show that our solution saves a significant amount of test time under the power constraint, and the hardware overhead is low.Then the paper proposes a new BIST strategy based on the state seeds. The main idea is that with the state seeds'statistic, we found that the usefull state and their test time are both very low, so we just store them on the chip memory and test the circuit. The experiments results show that the test solution is very great.