Research Of The Key Technology For Low-Power TLB Design

Along with the extensive application of the computer, the requirement of memory capability in the computer is also more and more large. Although the modern memory technique is developed rapidly, but the performance of CPU is enhanced about 55% every year. This results in that the speed CPU run at is faster than that of the memory accessing because of the memory's annually 7% exaltation speed. Therefore the computer engineers use memory hierarchy to solve this question. TLB is the address translation part for CACHE which is placed most closely to CPU in the memory hierarchy. So, the speed is the most important thing to design TLB.Due to the number of the transistors in the unit chip area increases exponentially, the power dissipation of the microprocessor consumes rises continuing. And the TLB uses fully associative placement generally, this make it become the focus of the microprocessor power dissipation. Therefore, how to lower the power dissipation of TLB is also important.The microprocessor design complicate increasingly, but the number of the professional design engineer is very short, and the design level of microprocessor in our country trailed the world leader, all of these decide that our architects must pay attention to the reusability and expandability when they design microprocessor to shorten the gap between our country and the other. As a result, in this topic about study design of the TLB, the reusability and expandability become a point equally.This topic emphasizes in these three aspects to research the key technique of TLB design, from the microarchitecture study to the realization of the concrete electric circuit and layout realization, in all of these the abundant results has been obtained. In the foundation of the design and realization, the full test verification to the contents design has been carried on, and the test results have been analyzed in detail. This topic obtained the important research results totally as follows:1. At the microarchitecture , the architecture of TLB is studied deeply, a new precomparison TLB structure is designed to lower the power dissipation observably consumed by TLB, and the detailed emulation for this new structure has been carried on. The result shows that compare with traditional few TLB structures, this kind of structure acquires very observable effect.2. The logic structure of CAM is analyzed, and a new type CAM electric circuit that using a kind of classified NOR structure is presented. The advantage of this kind of structure is that it can adapt to the extension of different request for the application of CAM continuously currently. This structure can satisfy many different requirements, and can be designed or compounded the CAM needed. So this structure sufficiently achieves the reusability and expandability for CAM design.3. A SRAM has been designed to combine with the aboved CAM, and with some control electric circuits to produce a TLB. In this article, the detailed test to the CAM, SRAM and TLB, has been carried on, and the exploitation of test code is introduced. At the same time, the TLB has been simulated with SPICE models. The simulation results have...