The Research Of SoC Test Data Compression Method Based On Huffman Coding

Testing has become an essential part of Integrated Circuit (IC) implementation processes. With the increasing scale of IC, testing is becoming more and more complex. The cost of testing IC occupying the total cost of semiconductor products is increasing. Though System-on-Chip (SoC) which adopts the technology-based IP cores reused has been significantly enhancing the productivity of IC, reducing the time of development period, accelerating the time to market and so on, it has brought a lot of problems simultaneously. The ever-increasing integration level of SoC leads to increase the amount of test data and accelerate the growth of clock frequency which has brought about a severe test to the traditional automatic test equipment (ATE) memory and bandwidth.At present test data compression technique is an effective approach to solve the problem of SoC testing. This dissertation proposes two new test data compression schemes based on Huffman coding by analyzing a variety of efficient test data compression methods. The contents are as follows:(1) This dissertation describes the technology-based SoC, SoC testing methods and the problems of SoC testing. Then it focuses on the analysis and summary of several methods about test data based on Huffman coding compression.(2) This dissertation proposes a method on a test data compression scheme based on Variable-length Input Huffman Coding in SoC. The runs of 0's and 1's in test sequences are directly encoded through the method of partial runs reversing. We use a Huffman code to identify the operation of reversing. The runs of 0's and 1's whose lengths are equal use the same code. So it can reduce the number of the short runs. Its decompression architecture comprises a Huffman decoder,a control and generator unit(CUT). But it does not require a separate CSR.(3) This dissertation proposes a method on a test data compression scheme based on Optimal Selective Huffman Coding. It can increase compression ratio by improving the correlation between the data block after a test set is classified as fixed-length data blocks. We select the data blocks which have only a few bits different with the distinct blocks in all unencoded data blocks. Then we use the method to mark the address for the different bits, reusing the high frequency distinct blocks. So we can improve the compression ratio by increasing the frequency of some distinct blocks.For the ISCAS'89 benchmark circuit,the experimental results show that the two coding methods proposed in this dissertation can effectively compress the test data set and have general applicability.