Research On Test Data Compression Technology Based On SoC

The application of Very Deep Sub-Micron (VDSM) technology increases the density of chips greatly. IC design is being quickly transformed into SoC (System-On-a-Chip) design. SoC has incomparable advantages not only in developing period, but also in the system function and performance. However, with the increase in the number of IP cores integrated, and its function becoming more complex, test data volume and test power consumption for SoC grow quickly, test access is also more difficult. All the cases pose more challenges for SoC test.The problem of SoC test is drawing more and more attention, and test data compression is a feasible way to solve this problem. It can be used to decrease the SoC test data volume. While testing, the compressed data can be decompressed to the original test vectors by the decoding circuit, then the original vectors are put into the CUT(Circuit Under Test) to finish the test.Thus test data compression of SoC is studied in this dissertation. The related theories of SoC test and SoC test data compression technology are described in detail. Then the advantages and disadvantages of several existing typical methods are analysed. Also the applicability of every method is summarized and some improvements are made based on them.An improved FDR codes compression method based on precomputed don't care bits is put forward in this dissertation. It is a coding method with highly comprehensive performance and it makes some improvements on FDR codes which is an excellent method in test data compression area. Because of the disadvantage of FDR codes which encodes run-length of 0 and can not get a high compression ratio for successive 1, a compression method is put forward encoding run-length of 0 and 1 simultaneously. Besides, to get higher compression ratio and lower test power dissipation, a precomputation method is put forward to appoint don't care bits by former and latter data bits. Then the encoding algorithm and decoding circuit are given accordingly. At last, the specialization method for don't care bits is applied to state reversal run length codes and some improvements are made in precomputation accordingly.To verify the accuracy and usefulness of the proposed method in the dissertation, then a series of experiments are made. From the results of ISCAS-89 benchmark, the method comes to the result of the expectation.