Researches On VLSI Design Of Video Intra Decoding In H.264/AVC

With the coming of the 21st century, man is entering into a brand-newmultimedia age.Digital Video Processing, as the most important, expressive andcomplex one in multimedia, has progressed quite a lot.The new video compressionstandard H.264/MPEG-4 part 10 AVC (H.264/AVC or H.264 for short below) hassignificant improvement over all previous ones in coding quality and compression ratio.With the same visual perceptive quality, H.264/AVC provides gains in compressionefficiency of up to 50% over a wide range of bit rates and video resolutions compared toprevious standards.And H.264/AVC also has better network-friendly speciality than theother standards. The H.264/AVC standard indicates the latest progress in videocompression.H.264/AVC improves the key components of coding structure based on hybridvideo coding framework.For example,it adds multi frame motion estimation,intraprediction, context-based adaptive variable length coding,4×4 integer transform, etc. Asa whole, the improvement in performance leads to remarkably higher computationalcomplexity in the new standard.In this thesis, the H.264/AVC video compression standard is introduced, and theresearch on the hardware implementation of high definition H.264/AVC VideoReal-time decoder is also represented.This thesis mainly focuses on transformcoefficient decoding process(including inverse transform coefficient scanning process,inverse quantization,inverse transform and picture construction process prior todeblocking filter process) and intra prediction process,then presents a VLSI architecturewith pipeline and parallel operations.The three parts of transform coefficient decodingprocess are dealed with pipeline operation, and Intra prediction works in parallel withinverse scan, inverse quantization and inverse transform.Thus,it could save a lot of timeand enhance the processing speed.The worst case of Intra decoding one macroblock isjust 877 clk,which could meet the real time request. Then, this modules are allactualized by VerilogHDL.Finally, the scheme has been successfully implemented onALTERA's STRATIXⅡFPGA device EP2S60F1020C5,and the system has got verygood real-time performce.