Research On VLSI Architecture Of An Intra Coding Loop Based On HEVC

With the rapid development of video industry,HD and UHD videos have also been widely used,leading to a sharp increase in the amount of video data.JCT-VC has formulated a new generation of video coding standard——High Efficiency Video Coding(HEVC).The coding performance of HEVC has almosted doubled comparing to H.264/AVC.As a key module of HEVC,intra coding plays an important role in the improvement of the coding performance by adopting flexible quadtree division structure,more refined intra prediction modes and other techniques.However,the intra coding process not only involves huge computation but also has strong data dependency.The processing of each Prediction Unit(PU)depends on the results of its previous PU,which has an extremly bad influence on the pipelined hardware implementation of HEVC intra coding,decreasing the throughput of intra coding process.This posts a great chanllenge for the real-time intra coding of HD video.In this thesis,a research on HEVC intra coding process is conducted from the perspective of hardware implementation.The main contents are as follows:First,an analysis of the data dependency in the intra coding process is carried out.Data dependency means feedback or loop.There is a loop in the intra coding process.Every PU needs to be predicted,transformed,quantized,dequantized,inverse-transformed and so on to get its best intra prediction mode along with the generation of the corresponding reconstruction pixels.And the next PU has to obtain the reconstruction pixels from its adjacent PUs as the reference samples before it can be predicted.From the perspective of hardware implementaion,it will cause idle cycles in the pipeline,leading to a low utilizing rate of hardware resources,decreasing the throughput of the whole intra coding loop.Through research on the parallel processing techniques of HEVC encoding,a hardware-oriented CTU processing order is proposed based on Wave-Front Parallel Processsing and a VLSI architecture of HEVC intra coding loop is designed,effectively solving the low throughput issue resulted from the strong data denpendency.Besides,because of this new CTU processing order involves two CTU in a interleaved manner,the storage resources will doubled without being optimized.A thorough analysis of its storage resources is carried on,reducing as much storage resources as possible,leading to a moderate increase of storage resources.Based on this thesis,the throughput of the whole intra coding loop increases by 57.6%.The hardware resource of the reconstruction-pixel-generate module and the reference-sample-select module only increases by 31.3% and that of other modules stays the same.These two modules can support the real-time HEVC intra coding of 4K@60fps videos.