The Research And Implementation Of Intra-frame Prediction Decoding For H.264 Standard

The video coding is the execution of decor-relation,with the compression technique,for intra-frame encoding,inter-frame encoding and entropy encoding etc.By reducing the redundant information,it will realize the transmission and storage of high-information image with low data.As the wide application of network video,the video compression technology has witnessed a rapid development.Being a typical example of it,the standard of H.264 announced by Joint Video Team in 2003,is popularly with its high compressibility rate and excellent network affinity.Thus,the hardware implementation of the H.264 video compression standard has been being the hot-spot in the researching field of video.Based on the theory of intra-frame decoding,the thesis takes the Baseline profile of intra-frame prediction decoding in H.264 standard as the research object and designs the macro-block level hardware decoding circuit.The sample formats adopted in the research are the formats of 4:2:0,4:4:4 and 4:2:2,which can to some extent pave the way for future study of main profile and extended profile.In the design,the intra-frame decoding system will be completed by modular design,and the sequential control between different modules will be gained by two-level state machine.Besides,the intra-frame decoding with different sample formats are to be realized through the calculating units in the reusable Plane Mode,which will greatly reduce the waste of hardware.Furthermore,the memory module of hierarchical design is to be used in the research and the reading and writing of the parameter pixels in memory will be achieved by windows proceedings.Applying the 4×4 block as the basic calculating unit,17 different sorts of calculating units in predicting mode will be synthesized into 10 kinds.Applying the Verilog HDL language for hardware circuit design,the research will be verified by the software of ModelS im6.6d.After validation,the result of hardware decoding will be compared with the result of the software decoding in JM reference model to prove the validity of the system function.In the end,based on the DC synthesis of SIMC 0.18 ?m technology,a frequency of 150MHz will be achieved in the design,which can satisfy with the requirements of the real-time decoding of 1080P format(1920*1080,60 frames/second,various compressive formats).The innovativeness and uniqueness mainly lie in the three aspects.(1)The hardware design will be carried out with 4×4 block as the basic unit,and all of the prediction calculations will be processed in the basic unit.Prediction and the rebuilt of pixel will be carried out with different reference pixels and reusable units dependent on different prediction modules,which can lower the wastage of hardware and effectively save more space.(2)The design will be able to process the intra-frame decoding with various sample formats,optimize the calculation of Plane Model with brightness prediction or chromaticity prediction,and thus introduce a reusable structure within the Plane Model.And the preprocessing of the very mode will increase the efficiency of intra-frame prediction decoding.(3)By adopting the structure of three-level pipeline in two-level state machine,along with the alternate decoding of the brightness serial and chromaticity parallel the pixel prediction and rebuilt of intra-frame decoding will be realized in the design.Achieving the real-time decoding of the formats of QCIF,CIF,720P and 1080P supported by the intra-frame decoder,the design will thus enjoy a better accessibility and versatility.