Research On Channel Decoding Algorithm And VLSI Design Based On Hybrid Stochstic Computing

The modern society have entered an era of explosive growth in information,where the massive demand for data processing and transmission presents many challenges to modern communication systems,such as high efficiency,high throughput,and high reliability.Channel coding technology is one of the cornerstone technologies in communication systems,and high-performance channel coding provides a guarantee for achieving high-reliability communication.Meanwhile,low-complexity and low-latency channel decoding algorithms are key to achieving high-efficiency and high-throughput communication systems.However,on the one hand,large-scale parallel decoding is widely used to achieve high throughput,but the area and power consumption of the VLSI chips that serve as the carrier of decoding algorithms also increase exponentially.On the other hand,with the development of the Internet of Things,wireless communication systems are widely deployed in many resource-constrained mobile terminal devices,and can only support low-complexity and low-power consumption decoding systems.Therefore,how to solve the contradiction between high throughput and low hardware resource costs,and simultaneously consider high throughput and high hardware efficiency while ensuring high performance,has become an urgent and challenging research topic in the design and implementation of decoding algorithms.This article aims to research high-performance,low-latency,and low-complexity decoding algorithms.Specifically,it focuses on LDPC codes,polar codes,and Turbo codes,which are widely used in various communication standards.For each of these codes,a new decoding algorithm based on hybrid stochastic computing is proposed to achieve high performance,high throughput,and high hardware efficiency,along with its VLSI implementation.The main contributions of this article are summarized as follows:1.A segmented HS LDPC decoding algorithm is proposed to overcome the drawbacks of traditional LDPC decoding algorithms,such as high complexity,long critical paths,and wire congestion,as well as the poor performance,slow convergence speed,and limited applicability of sttochastic LDPC decoding algorithms.The proposed algorithm combines the traditional MSA with the probability decoding algorithm,inheriting the advantages of both methods,namely,the good performance and fast convergence speed of the traditional algorithm,as well as the low complexity of the stochastic decoding algorithm.Furthermore,by using a specific sequence of random numbers,the proposed algorithm enhances the MSA without increasing its complexity,significantly improving the decoding performance.Simulation results demonstrate that the segmented HS decoding algorithm can achieve similar performance and convergence speed as the traditional decoding algorithm,and can be applied to various code rates and lengths,as well as design requirements for partial parallel decoding.Based on the segmented HS decoding algorithm,an LDPC decoder from the IEEE 802.3an standard is designed and implemented in this paper.The comprehensive results show that the designed LDPC decoder achieves the highest throughput and decent hardware efficiency among published literature.2.A BSU-HS decoding algorithm is proposed to improve the decoding performance,throughput,and hardware efficiency of HS decoding algorithms.This algorithm addresses the issue of high conversion errors and latency due to low conversion efficiency from binary field to stochastic field in segmented HS decoding algorithms.A probability tracker based on SR update is introduced to achieve more efficient and fine-grained iterative updates.Two optimization strategies are proposed to balance the tracking accuracy and speed of the probability tracker for fast convergence and performance improvement.Simulation analysis shows that the BSU-HS decoding algorithm outperforms traditional binary decoding algorithms,and this performance improvement increases as the code rate decreases.An IEEE 802.3an standard LDPC decoder is designed and tested using BSU-HS,achieving three times the throughput and twice the hardware efficiency of the best-known results in existing literature,while its normalized power consumption is only half that of the best result.3.A Do PE-HS decoding algorithm is proposed to overcome the poor performance of BP algorithms in Polar decoding by utilizing the appropriate randomness of HS decoding algorithms.This randomness helps overcome the convergence issues caused by a large number of short cycles in the factor graph of Polar codes that make BP algorithms difficult to converge.Do PE provides a way for HS algorithms to be correctly applied to BP Polar decoding algorithms based on layered factor graphs.Multiple strategies for random number iteration are proposed to meet the coherence requirements of HS decoding algorithms between random numbers while achieving a balance between decoding performance,decoding complexity,and convergence speed.A probability tracker based on segmented sequence is introduced to control the accuracy of each iteration and achieve appropriate randomness.A corresponding parallel Do PE structure is proposed to minimize decoding latency.Simulation analysis shows that Do PE-HS decoding can achieve much better decoding performance and faster convergence than traditional BP algorithms.Complexity analysis shows that for the same decoding performance and hardware efficiency,the decoding latency of the Do PE-HS decoder is only one-quarter that of the SCL decoder.4.A concept of stochastic quantization is proposed and applied to the state metric storage compression algorithm of Turbo decoding to achieve high-performance,highcompression ratio state metric storage compression with extremely low complexity.A specific random number sequence is selected to meet the criteria of unbiased quantization for stochastic quantization,and SR update is introduced into the extrinsic information update of the stochastic quantization-based Turbo decoding algorithm to improve its decoding performance under low quantization bit widths.Simulation and synthesis results show that the proposed algorithm reduces the bit width of the state metric that needs to be stored by nearly half without sacrificing performance,and the complexity of both the compression and recovery algorithms is much lower than that of existing state metric compression algorithms.This article has achieved high-performance,high-throughput,and high-hardware efficiency decoding of the current mainstream channel coding based on a novel hybrid probability calculation through the four aforementioned works.It provides a novel and feasible solution for the high standards and requirements of modern communication systems for channel coding technology.