Researches On VLSI Design And Implementation Of Intra Prediction In H.264 Video Coding

With the rapid development of information technology, we have got to the multimedia era. Multimedia telecommunication has developed as one of the most important way for man to communicate with each other. H.264 has been widely accepted as the best video standard for its high compression ratio, good image quality and the advantages of network friendly and high efficiency of resist error coding.Compared with the early video compression standard, H.264 has imported many new algorithms,for instance, the multi-mode motion estimation, Intraprediction, flexible length coding based on the image content,4x4 two-dimension transform,and so on. However,with the H.264 standard, the improved image quality is on the high cost of the computation complexion.Thus, it is of great significance to design video codec systems based on FPGA and some mature chip.This paper introduces the H.264/AVC video compression standard and the researches on VLSI design of the video intra coding, mainly about the deeply study of the Intraprediction,and bring up a structure on VLSI with the parallelism disposation and flow design,which has saved much of the computation time and the system resource.The total time of the intraprediction for one macroblock is 1136 clock cycles,which meet the requirement of the real-time decoding.The writer has verified and realized the module with the VerilogHDL language on the chip of Xinlinx Virtex 5,and got the good efficiency.