A Fast Algorithm For H.264/AVC Intra Prediction Encoder And VLSI Implementation Of Decoder

The new video compression standard H.264/AVC has significant improvement over all previous ones in coding quality and compression ratio. With the same visual perceptive quality, H.264/AVC gains in compression efficiency of up to 50% over a wide range of bit rates and video resolutions compared to previous standards, and also has better network-friendly speciality than the other standards. H.264/AVC improves the key components of coding structure based on hybrid video coding framework. For example, it adds multiple frame motion estimation, intra prediction, context-based adaptive variable length coding, 4×4 integer transform, etc. In a word, the improvement in performance leads to remarkably higher computational complexity in the new standard.In this thesis, the H.264/AVC video compression standard is introduced, and also the research on a fast algorithm for H.264 intra prediction encoder and the VLSI implementation of decoder. In the encoder, a fast algorithm is proposed in this paper. The algorithm decreases the selection range of prediction type based on the analysis of quantification parameter Qp. By the judgment of all-zero blocks or near-all-zero blocks, prediction can be early terminated. The computational complexity can be further reduced by the use of the directional neighborhood of the optimal mode or the sub-optimal prediction mode. Experimental results show that the proposed algorithm can reduce 40%~96% computational complexity of the intra prediction while degradation of the image quality is negligible.More attention is paid to the VLSI implement for the decoder part. An algorithm for H.264 decoder suitable for hardware is presented based on the elaborate analysis of macroblock-adaptive frame-field intra prediction and residual inverse transaction. By using pipeline and decompose algorithm, the resource of hardware implementation are reduced, and the parallelizability of H.264 hardware system enhances. The experimental results show that the decoder system can realize real time decoding completely. The system has been implemented on FPGA, and working frequency can reach 80MHz.