Research On Decoding Algorithm And Architecture Design For Polar Codes

Polar codes have attracted a lot of academic interest in the past ten years for their capacity-achieving property.With the advantage of regular encoding structure,explicit construction method and low-complexity decoding algorithm,they have been selected for the control channel by 5G standards and have a broad application prospect.However,in current researches,the polar codes with short or moderate code lengths still fall short in error-correction performance,decoding latency and throughput.Aiming at solving these problems,we modified the decoding algorithm to improve the performance,adopted parallel calculation to improve the throughput and improved the area efficiency by sharing common hardware resources in this paper.The main research results are summarized as follows:1.In order to prevent the error propagation in the successive cancellation(SC)decoding,we proposed a concatenated polar codes,which only provide extra protection to some critical information bits,basing on the study of the existing concatenated schemes.The critical set is iteratively constructed with the constrain of overall code rate to reduce the increase of internal code rate and improve the error-correction performance.In the design of corresponding decoder,multiple parallel decoding cores are adopted to decode inner polar codes and share the common control module and partial memory.As for the outer codes,the BCH codes with the same code rate and performance are adopted to realize fast decoding by Look-up table.The experimental results show that the decoding latency of the decoder is reduced while the area efficiency is improved.2.To overcome the limitation of correcting multiple erroneous bits,the relationship between the decoding path metrics and the correctness of bit-flipping is evaluated.Based on this relevance,we propose a path metric aided bit-flipping decoding algorithm,in which the bit-flipping list is generated based on both log likelihood ratio(LLR)based path metric and bit-flipping metric.By using this bit-flipping list,the accuracy of bitflipping can be improved,while the number of decoding attempts can be much reduced.In the design of corresponding decoder,since there is no data-dependence between multiple decoding attempts,each decoding attempt can be excuted in parallel according to its own decoding instruction and share the common processing elements.By this way,the overall decoidng efficiency is improved while the decoding latency is reduced.3.To solve the uncertainty of decoding latency of bit-flipping algorithm,a hybrid decoding algorithm combining bit-flipping and list decoding is proposed.In this decoding algorithm,the path splitting in successive cancellation list(SCL)decoding can be viewed as parallel multi-bit flipping,while the path matric can be viewed as the feedback of the effectiveness of previous bit-flipping bits.Different from traditional SCL decoding,the decoding candidates will be pruned according to their path metrics before path splitting.The bit-flipping set is generated based on the statistical error probability of each subchannels.To further reduce the size of bit-flipping set,the convolutional polar codes are adopted in our decoding algorithm,since their high polarizaiton rate.Simulation results show that our decoding algorithm can much improve the error-correction performance while ensuring the certainty of decoding latency.4.To improve the utilization of processing elements in current SC and SCL hybrid decoder,a hybrid multicore parallel decoder controlled by decoding instruction is proposed.In this decoder,multiple decoding cores can work in parallel,while the decoding cores can independently excute SC decoding or joint together to excute SCL decoding.Each decoding core excute decoding calculation according to its own decoding instruction and share common processing array.The constant receiving rate is supported by using the input buffer,and the other modules in the decoder are modified to meet the instruction decoding process.Besides,a link-level simulation platform is established to optimize the design parameters of each module in the decoder.The experimental results show that the design of hybrid decoder improve the utilization of processing elements as well as the overall area efficiency.