Research Of Design Methodology For FPGA Dynamic Self-Reconfiguration System

Processor mode and ASIC(Application Specific Integerated Circuit) mode are current mainstream computing modes. The processor computing mode could flexiblely finish variety of computing tasks, but performance is its shortcomings. On the contray, the ASIC computing mode could achieve high performance, but it cannot flexiblely deal with changed computing tasks. FPGA's(Field Programmable Gate Array) programmability and high parallel execution efficiency have both software flexibility and hardware high-performance, causing widespread concern.This research which is funded by the cooperation project of Dalian University of Technology and Intel Co. studies a dynamic self-reconfiguration system design methodology, using the embedded hard microprocessor to control the implementation of FPGA dynamic reconfiguration. This paper selects Xilinx Co. Virtex-II Pro FPGA as carrier, studies the configuration principles, configuration structure and configuration process of SRAM-technology-based FPGA, and analyzes the EAPR (Early Access Partial Reconfiguration) design method. Combining practice and some Xilinx's latest FPGA development tools, this paper proposes a dynamic self-reconfiguration system design method, and develop a OPB_DCR_SOCKET module to simplify the design of reconfigurable IP cores. This method provides a methodological guide for complex system design with dyanmic reconfiguration technology.This paper also designed a multimedia information processing system using the improved dynamic self-reconfiguration system design method. The video processing module, audio processing module and arithmetic operation module can be dynamically configured under the control of microprocessor embedded in the FPGA, without affecting other modules' normal operation. This design verified the validity of the design method and also exhibited the superiority of dynamic reconfiguration technology in the hardware resource time-sharing. Finally, this paper tested the reconfiguration time of the multimedia processing system, analyzed the experiment result and discussed some optimization method.