The Reverse Design And Fabrication Of Pulse Width Modulation Device

Pulse Width Modulation device is a circuit which can produce square wave signal with fixed period and adjustable pulse duration ratio (pulse width). The chip is an integrated circuit chip which is researched by Northeastern Microelectronics Research Institute (47 Institute). This article is completed in the Institute. The circuit is used in a part of driving circuit of phase control line radar ferrite phase shifter and is also used in the other power amplifiers.Pulse Width Modulation device chip is designed by the reverse design method. After the original chip is dissected, photomicrographed, conjoined, the schematic is extracted. The extracted schematic is simulated and the layout is drawn uses the excellent Cadence tool software. And the simulation results accord with the circuit function. At last the chip is fabricated successfully in the process line of the Institute.The original chip is P-well silicon gate CMOS process and single metal. Its characteristic dimension is 4pm. It operates under the 9V power voltage. The static current is lower than 2mA. The operation frequency is 2KHz. The input level is compatible with TTL level. The circuits conclude an 8-bit digital-to-analog converter, two voltage comparators, two latches, logic combination circuits, etc. R-2R ladder resistor networks are used in the digital-to-analog converter. The construction not only is beneficial to improve the matching precision of resistors, but also has small layout area. The others are basic CMOS cell circuits. A reset pulse signal R and a set pulse signal S control reset and set driver outputs which drive the ferrite phase shifter to reset and set. The whole chip includes about 900 transistors and is a mixed small scale application specific integrated circuit chip.The chip layout redesigns adopt 3μm P-well silicon gate single metal CMOS layout design rules. Logic combination circuit layout adopts standard cell design which reduces chip area on the whole. At the same time, to prevent the generation of latch-up, guard rings are added around the large dimension digital output inverter PMOS and NMOS transistors of the circuits.