Research On Latch Up Effect In Power ICs

Technology advances in VLSI and high-voltage power transistors have made possible the development of Power Integrated Circuit (PIC). In applications such as display driving, telecommunications, and motor control systems, the use of PIC's can significantly reduce system cost and improve reliability. In order to reduce the development time and cost, process compatibility with an existing low-voltage CMOS process is highly desirable. Latch-up is a ubiquitous problem in PIC.It is analyze from the causes of Latch-up effect in this paper. Firstly, the CMOS Latch-up including the background, modeling and the avoidance techniques is expounded. Secondly, the latch-up structure in PIC is advanced. Then, the software tsuprem4 and medici are used to simulate the latch-up effect. Based on the simulation results, the best latch-up avoidance technique is found: the guard rings including the majority guard ring and the minority guard ring are added in the more reasonable layout. Consequently, the layout design rules which prevent the latch-up in PIC are summarized. In the end, the latch-up test is introduced and the validity of the latch-up avoidance technique in PIC is proved by the test results.This paper is studied about the Latch-up effect in PIC. It is based on the reasonable layout, and at the same time the new protected structure is added. At last, it is passed in the practical test, which is proved these measures are in effect. Therefore, it is accumulated lots of experience in Latch-up free in PIC.