The Critical Path Optimization Based On Pulsed-latch

The rapid development of integrated circuit making the chip have a higher integration and more outstanding performance, but the difficulty of timing convergence of the chip is becoming more and more obvious. In this paper, we research how to effectively optimize the critical path to achieve timing closure and reduce the time-to-market of the chip based on the physical design of the L_unit in the YHFT-DX chip.The YHFT-DX chip required to reache 1 GHZ clock frequency under the worst case condition and 40 nm process. The structure of the L_unit is very complex as an imorptant part of the YHFT-DX chip. There are some critical path in the chip after several times of optimization.In order to remove these critical path quickly, we use the pulsed-latch with lower-delay-time to replace the registers on the critical path.In the paper, we designed the experiments required pulsed-latch by using the full-custom design according to the principle of pulsed-latch and the layout of the register with scanning function which is a standard cell. After the back-end verification, the delay of pulsed-latch reduced by 51.9% compared with the standard cell with similar function.Then, we realized horizontal structure multi-bit pulsed-latches by grouping one-bit pulsed-latch according to the one-bit pulsed-latch structure characteristics. Further more, we designed the vertical structure multi-bit pulsed-latches on the purpose of preventing the IR-drop on the interconnect wire in the circuit. Comparing with the standard cell with same function, the multi-bit pulsed-latches which is three or four or five bit not only having a advantage of low-delay-time but also having lower power consumption and unit area. And the experimental results proved that the multi-bit pulsed-latch with the output load of 30 FF, using M3~M7 as interconnect wire, the interconnect wire delay of 30 um long is about 2ps.Third, According to the factors causing the timing violation, we proposed the optization method by using the full-custom designed one-bit pulsed-latch to replace the registers on the critical path, and then transform the optimization method into the automatic processing algorithm and tcl scripts. After analysis the advantages of different replacement process and implement the experiments, the final results show that the critical path is reduced by 99.45% and the whole circuit timing performance upgrade 12% measured by the number of violation path from register to register and the worst neg- ative slack when replace the registers on the placement stage.Finally, we proposed a preliminary method by using multi-bit pulsed-latch replace the registers on the critical path according to the advantages and characteristics of multi-bit pulsed-latch. We determined the final implementation plan after solved the existing problems in the preliminary method based on the previous chapters experimental results. And also we transformed the method into an optimization algorithm and automatic processing tcl scripts so that the practicability of the algorithm can be greatly improved. Experiment results show that the critical path is reduced by 99% and the whole circuit timing performance upgrade 11.4% measured by the number of violation path from register to register and the worst negative slack when using horizontal structure three-bit pulsed-latches replace the registers on the critical path within a 30 um rectangular. And it is the best time that replacing the register on the placement stage. In addition to we can obtain some superiority of 2.5% power consumption discount and 4.4% chip density decrease.A large number of experiments show that using the pulsed-latch can optimize the critical path effectivelly and accelerate the circuit timing convergence, further more the whole power consumption and chip density can be reduced in some extent.