Latch-up prevention and modeling of merged bipolar-MOS structures for BiCMOS applications

This thesis deals with the design, modeling and characterization of physically merged bipolar-MOS structures in BiCMOS technology. The use of the merged structures can result in significant area savings for BiCMOS digital circuits.;Latch-up in physically merged bipolar-MOS structures was studied analytically and numerically. An analytical latch-up model useful in calculating the latch-up voltage and current of the structures was proposed. The validity of the model was verified by 2-D numerical simulations. The model can provide guidelines for the design of latch-up free merged structures. Layout rules for latch-up prevention were generated. Merged test structures designed using these layout rules were implemented using a standard 0.8;Analytical models useful in describing the static and dynamic characteristics of the merged structures were developed. The models provide insight into the structure's performance and can be used to optimize the design of merged BiCMOS structures. An HSPICE model for the merged structures was also developed and its validity and accuracy were verified by experiments and 2-D simulations. The model can be used to design and optimized merged BiCMOS circuits.;To demonstrate the advantage of using the merged structures, BiCMOS gates using merged and separate devices were compared. The gates using merged devices occupy much smaller (32%) silicon area and operate slightly faster than the equivalent gates using separate devices.