Research Of Image Compression System Based On FPGA

Recently, with the rapid development of electronic technology,the digital image processing technology have been matured gradually. Digital image processing has already expanded from the visible spectrum to each stage of spectrum, from the static image to the motive image, and from interior to exterior in object. Therefore, the research of chip that can encode and decode becomes the center of multimedia technology.Compared with traditional MCU, DSP, the advantage of FPGA is speed fast and configuration flexible. So this article selects Altera Corporation's Cyclone II EP2C70F896C6 as image compression core chip and makes use of other resources of development board to achieve JPEG Baseline compression system. The two-dimensional discrete cosine transformation (2-D DCT) in JPEG compression algorithm is achieved based on the algorithm of row-column decomposition. In order to reduce the computational complexity, one-dimensional discrete cosine transformation is realized by fast algorithm. In order to improve the throughput of the module, the pipelining technology is taken. To improve compression system performance, the color space conversion is completed by the custom instruction. In order to communicate between AVALON bus and image sample module and between AVALON bus and image display module, Master Write Transfer with Wait Requests and Master Pipelined Read Transfer Modules that comply with the rules of AVALON bus are designed and has realized the image data automatic storage and display. Finally, the entire hardware system is made in the SOPC Builder. Dimensional discrete cosine transformation module and Master Write Transfer with Wait Requests and Master Pipelined Read Transfer modules are added in the system in the way of custom peripheral, color space conversion is integrated into the CPU in the way of custom instruction. Compiling and debugging of the system's software is completed in NIos II IDE.This paper takes advantage of the idea hardware and software co-design of SOPC and does a useful the exploration of attempt for design of complex system on chip (SOC), which has certain significance for the rapid construction of real-time video compression chip design.