The Design Of IP Camera Controller Based On FPGA

In recent years, with the development of network technology, digital video monitoring has entered the Internet age, network-based video monitor IP Camera has become a hotspot of current research. By using video-compression technology, we can achieve the real-time vedio transmission featuring small dataset and high-quality through the Internet.With further enhancement of the Internet transmission technology, gigabit bandwidth fiber optic network is widely used in financial network monitoring and Safe City projects to effectively support the transmission of high quality video through the Internet. Proceed from the development trend of techonology, with the increase of IC vendors, an increasing number of enterprises have participated in the R&D of IP Camera. They have come up with numerous designs, and the competition is fierce. However, the domestic market is far from mature. Mainstream chip platforms in the market, Winbond, Nuvoton, Hass, Ambarella, etc., use integrated chips or DSP, FPGA design and implement are hardly used. Therefore, the usage of FPGA in the design and research of IP Camera has tremendous value in research and in market.This paper contains the following four sections. First, the video image acquisition, processing and storage by FPGA. Second, a customized IP core, integrated with a data conversion interface controller and a network transmission interface controller. The data conversion module implements the data transmission between Nios II processor and SDRAM memory. The Network transmission module implements the data transmission of the Nios II processor through the Internet. SOPC technology will be used to integrate all these modules, including the customized IP core, into a system. Third, the software realization of algorithms for image data processing, DM9000 A NIC driver and UDP communication. Fourth, receiving and displaying the video in a client. The paper is concluded by an overall test of the entire system. The remote monitor can correctly receive and display the images collected by the CMOS camera, which justifies the feasibility of the system.