Research And Design Of The JPEG Encoder System On SOPC

JPEG is a commonly used digital image compression algorithm officially known as ISO/IEC Standard 10918. JPEG has been widely used in multimedia communication for its excellent performance on compressing continouse tone still image. Along with the development in mobile termination, multimedia, Internet network, Correspondence as well as picture scanning technology, real time processing of image data gets more and more important. Software based data processing usually has difficult to meet the timely requirements of the high-speed realtime systems. Therefore it has been practical application to realize picture processing algorithm with hardware.SOPC is a system on a single chip based on large-scale FPGA. SOPC includes soft-core or hard-core CPU,memory,I/O and programmable logic resource, which has all the advantage of SOC,PLD and FPGA. Developing a SOPC system is a process of hardware and software co-design. Hardware and software co-design enable the parallel developing of both hardware and software. Implementation of this co-design can improve the development efficiency and shorten the development period. Another advantage is to achieve objective with different means by analyzing each module's features and restriction.This thesis consists of designing and implementing a JPEG encoder system that is compatiable with JPEG baseline mode in standard hardware description language Verilog based on SOPC. Though optimizing structures, with conditions of efficiently using of hardware resource, the ultility of the parallel algorithm is exploited more efficitenly. The concept of JPEG baseline mode and the flow of SOPC design are firstly introduced. Disadvantages of traditional architecture are presented and discussed and an enhanced architecture is proposed. Design principle, structures and Verilog implementations of modules in this news architecture are described in detail. The result of synthesis and simulation indicate that the design can give a better performance on speed and resource using with less hardware resourc and a higher frequency, and can meet the requirement of realtime application of JPEG image processing.The system is consisted by image collection and image compression. The system completes Image collection by the CMOS image sensor. CMOS image sensor can directly export digital image according with the standard of CCIR601. Image compression using JPEG encoder IP core, the IP connected with Avalon interface, cooperated with the image pre-processing module, realizing image compression coding. Finally the efficiency of the software, custom instruction and custom interface are compared.