The Design And Implementation Of Video Image Rotation Based On FPGA

In embedded real-time processing applications,image rotation is widely used in various fields of social production and life, it is an important prerequisite of image preprocessing and detection. While the image processing system is required smaller,its real-time performance is put forward higher in today's industrial applications.In recent years,with the development of large scale integrated circuits,programmable logic device FPGA's internal resources have become increasingly diverse,more robust functionality.Thus, FPGA has been widely used in the current embedded real-time system.Meanwhile, FPGA has a great advantage of its powerful data processing with parallel and flexibility of the system based on SOPC in the field of image processing.Image processing is characterized by large amount of data processing,handling time-consuming,especially software based on embedded soft-core processing whose speed is a bottleneck in real-time systems.From this point of view, this paper completed the design and implementation of video image rotation based on FPGA.In this paper, hardware and software co-design thinking based on SOPC system is used.This system includes video capture module,video data storage module,video image rotation and its hardware acceleration module,video display module.The overall design of video iamge rotation based on FPGA structure, SOPC system. Using CORDIC algorithm, which replaces the trigonometric function computing in rotation matrix to realize hardware acceleration.Software module includes image rotation algorithm and bilinear interpolation algorithm. All modules are coordinated by the Avalon fabric bus.15-stage pipeline design of optimized CORDIC accelerator, which is used to do hardware acceleration in sin-cos calculation in rotation matrix, is designed. After a certain clock sycles,the CORDIC module will put out continuous input angle's sin-cos results. Importing this module to the ALU of the Nios core in custom instruction is also designed.The previous steps implements CORDIC accelerator.Considering of the limitations of CORDIC algorithm, this paper implements the optimized FPGA design. Expansion of the rotation cycle,arc-tangent function table storage optimization and simplification of scale correction factor reduce the number of ROM memory cells use without changing the algorithm accuracy and also expand the rotation cycle. Finally, the system's experimental result is given.The comparision of system before acceleration and after using optimized accelerator shows the system performance improves about 26 times. The system is accelerated ,its real-time performance is highly improved.And a large number of hardware and storage resources left can be used in other design and applications.This paper is featured by fully utilizing the thought of SOPC design and hardware acceleration in software.All modules are loaded to a FPGA microchip.Compared with other FPGA+MCU methods,it saves resources and system expenses. This system participated in Innovate Asia-Altera Design Contest 2009 and ranked an excellence award.