Real-time JPEG Encoding And Decoding System Based On FPGA

JPEG is the English abbreviation of Joint Picture Experts Group (Joint Picture Expert Group). It's a static image compression standard developed jointly by Inter- national Organization for Standardization (ISO) and CCITT. JPEG lossy compression based on DCT with high compression ratio characteristics is widely used in multimedia resources and bandwidth network which need to process great volume of data.Dynamic Image JPEG codec processing requires high image quality, real-time speed. The thesis is to do research aiming at the two requirements. The system consists of image compression server, which samples the dynamic images with a camera, processes them with JPEG encoder, then transport them through network, and image decompression client, which receives bitstream from the server and processes with JPEG decoder, recover the original images, then display them on VGA monitor. The result shows that the design can fully meet the real-time requirements.From the system perspective, the thesis firstly analyzes the system development platform and introduces the structural characteristics of FPGA as well as its design process and guiding principles. The later to be introduced is JPEG image compression technology development process and the reason why JPEG compression standards can achieve high quality images with high compression rate. Then the thesis focuses on the the characteristics of FPGA structure to achieve JPEG algorithm, introduces the design according to the sequence of encoding and decoding, including the FDCT and IDCT transform with improved DA algorithm, and optimized Huffman table frequency by frequency order, and the simplified structure of JPEG from the whole system aspect to improve the processing performance. Finally, the analysis aims at Nios embedded processor of customizable characteristics, translating image acquisition, JPEG image compression and network transmission into user-defined modules according to SOPC Builder Avalon bus requirements with the SOPC Builder, where the user-defined module can be added to the system, under the control of soft-core Nios Embedded. The whole system is achieved on a single FPGA chip (SOC) with real-time JPEG images encoding and decoding.JPEG algorithm as a FPGA hardware module with low power consumption, low production costs and stable performance, Image high image quality, has great advantages to apply to the high precision required for processing images frame by frame in long-range identification and tracking systems, and Early Nonlinear editing and digital film animation graphics production in the system of Radio and Television. There is a very great practical significanceto reduce costs and improve image processing speed. using FPGA to achieve JPEG encoding and decoding and further explore the advantage of FPGA in the Digital Image Processing, in-depth understanding of such hardware module design characteristics, this is the subject's most important of academic significance.