Bus Bridge Design Between AMBA And WISHBONE Bus Protocols

System On Chip has become the mainstream technique of digital VLSI design. Usually there are a number of IP modules on a SOC chip, including embedded CUP, DSP, function modules, memories and external interface modules. Master modules and slave modules are connected with on-chip buses in order to transfer control and data signals. The most commonly used on-chip bus protocol is AMBA 2.0 of ARM Ltd. All commercial IPs support it, so it has become the de facto standard of SOC bus protocol.The main advantage of SOC technique is IP reuse. To accomplish a SOC project, designers do not have to design all the modules from the beginning; they only need to integrate reusable IPs and part of their own designs together. But commercial IPs are expensive, purchase all the IPs in a SOC project is not cost-effective, only key modules like CPU or DSP require purchasing. Develop all other IPs is very time-consuming, so use free open source IPs became an appropriate choice.OpenCores is an organization which provides free open source IP cores. There are a lot of verified IPs downloadable on its website. But these IPs normally adopt WISHBONE bus protocol which is not compatible with AMBA. So if we want to integrate them into AMBA bus environment, there will be the need for signal transformation which translates different control signals and reconciles the timing difference between control and data signals.This paper uses Ethernet MAC IP on OpenCores'website as an example, and has designed a signal transform bus bridge between AMBA and WISHBONE bus. Ethernet MAC IP module can be connected to AMBA bus and function correctly through this bus bridge.This design uses Verilog HDL as coding language, and uses Synopsys VCS for simulation. Simulation results show the bus bridge works correctly under all kinds of bus requests, and the Ethernet MAC IP module which connected at the other side of the bus bridge works completely right. The bus bridge design is a success. Its advantages are very simple circuits, low latency and easy integration. It can be used on other IP cores which only have WISHBONE interface and make open source IPs from Opencores can be used very easily.