The Design And Implementation Of External Interface Circuit Based On LEON Processor

In recent years, as the rapid development of the semiconductor technique, the application of SoC(System on Chip) technique is becoming more and more popular. As a component of IC(integrate circuit) that has been designed, tested, IP core can be made repeated use of in SoC as well as in complicated ASIC(Application Specific Integrated Circuit). To connect diverse IP cores directly, OCB(On Chip Bus) is needed, which is able to complete the function of data transmission between IP cores through bus.LEON is a 32-bit RISC processor which is widely used in aerospace industry in recent years. It is a microprocessor core that is configurable, comprehensive and suitable for SOC design. Source code of LEON is consist of synthesizable VHDL code form and the performance of LEON is very good. Greater advantage is that LEON processor has open source code and follow the GNU LGPL agreement, anyone can downloads hardware code, development tools and documents on its website, then use them in their own ASIC projects.USB IP core is free resources which is available for download in international organization OpenCore. It uses the standard of WISHBONE bus while the internal bus of LEON processor follows the AMBA AHB bus protocol. If USB IP core which follows the WISHBONE bus can be mounted to LEON processor which follows the AMBA AHB bus protocol, resources on both buses LEON processor and USB IP core could communicate with each other. That is the implementation of the IP core effective reuse. So that the communication between the most widely used processors and the most convenient IP core will be easily, and design of SoC can be effectively simplified. In order to communicate the information between the two buses, the bridge must be used to transform the signals and timing. Therefore, this paper proposed and designed the AHB-WISHBONE bus bridge.This paper discripts and compares both AHB bus and WISHBONE bus protocols in detail, and analyses the differences between them in signals, time sequence,data width and data transmission. A resolution is proposed to eliminate these differences, based on which the design of AHB-WISHBONE bus bridge is put forward. A simulation of the AHB-WISHBONE bus bridge is completed in ModelSim. Result of the simulation shows that the AHB-WISHBONE bus bridge connects the USB IP core and the LEON processor successfully and accoplishs the function of data transmission between them.