Design Of AMBA/Wishbone Bus Bridge IP Core

With the rapid development of ultra large scale integrated circuit, the semiconductor industry entered the deep sub-micron era, which gives the development of SOC provided unprecedented opportunities and challenges. In SOC design of based on IP reuse, on-chip bus design is the most crucial issue. Current SOC on-chip bus is still in development stage and has no uniform standard, so the major manufacturers and organizations have launched their own on-chip bus standard.In SOC design, in order to integrate the different on-chip bus standard capable of data exchange and communications between IP, the corresponding bus bridge needed to implement interactions between them. Bus bridge completed conversion in different ends of the standard bus protocol, and achieve the bus interface signals match and timing adjustment between both ends of different bus. Bus bridge used to improve the reusability of the IP, so that the IP migration become easier of different bus architecture integration.The contents of this paper is: First, based on the current widespread use of AMBA bus and the Wishbone bus, by the analysis differences between AMBA bus protocol and the Wishbone bus protocol, given the overall design program of AMBA/Wishbone bus bridge. Second, using top-down design method and finite automat technology to build AMBA/Wishbone bus bridge, given the concrete realization of the various functional modules of bus bridge, including the bus bridge master protocol module, the bus bridge slave protocol module and the arbiter module of real-time arbitration algorithm. Finally by functional verification technology, designed verification platform and testing program based on the design, and Complete function verification of the design of AMBA/Wishbone bus bridge in ModelSim software. This verification results showed that AMBA/Wishbone bus bridge IP meet the design scheme requirements in reading, writing, multiple read and write and other function. Designed of The bus bridge has laid a good foundation to continue in-depth studing, and accumulated some experience for study on-chip bus interconnect technology.