The Design Of Avalon/Wishbone Bus Converter Bridge

Integrated circuit design has entered into the era of system on chip(SOC), the bus interconnect archinecture of System on board has also developed into a kind of hierarchy architecture-on chip bus (OCB).Different IPs are integrated on different types of OCB,the communication of different levels of OCB can use the bus bridge. As the technical development, the IP design and reuse of single bus system can not satisfy the need of application, an IP core can't be in general use under the different bus system. The commucation needs between different bus system come to be a new technological bottlenecks.There are many kinds of the OCB, the IP core, which is designed under single on chip bus protocol, can not be in general use with those which are designed under other bus protocol. To solve this problem, we can design different bus converter bridge between different kinds of bus protocol. Bus converter brideg means that to build a bridge which have the bridge function and also can realize the conversion between the bus protocols. The bus protocol here we mentioned is not bridge connection between system bus and periphal bus, but a bridge connection between different bus systems, which belongs to the protocol conversion between different system bus.The main task of this dissertation is to build Avalon/Wishbone bus converter bridge model which based on Avalon bus and Wishbone bus, also according to the studying and analyzing some bus protocols which are widely used and influenced. The design of bus converter bridge includes modules design Avalon slave state machine,Wishbone master state machine and buffer. This dissertation finally completes two bus converter bridge designs of different protocol, and also studies the general technique of functional verification which gets some experience for the studying of the on chip bus, and laid the foundation for the studying of bus converter bridge between multi-buses.