ADPLL Design For Application In SoC

An all-digital phase-locked loop (ADPLL) was implemented with SMIC 0.18μm CMOS technology library in this paper. First of all, based on the analysis of specific application requirements of PLL, the main performance specifications and system structure were defined, and the sub-module circuits were designed. Since phase frequency detector (PFD) and digital controlled oscillator (DCO) mainly determines the PLL's capture range, power consumption and jitter characteristics, this paper focuses on their optimal design. A kind of frequency tracking algorithm was proposed, which uses an adaptive search step, can achieve fast lock-in time. When implementing, Physical design flow of DC+Astro+Calibre is used, that is, firstly, using Verilog HDL for sub-modules description, and then using Design Compiler for synthesize, and then using Astro for placement and routing , finally using Calibre for DRC and LVS checks. The proposed ADPLL can be easily ported to different process as a soft intellectual property (IP) block, both design time and complexity can be reduced, which makes it very suitable for System-On-Chip (SoC) and system-level applications.The finished area of the ADPLL layout is 260μm×229μm(0.059mm2), and the equivalent gate count is 2612. According to simulation results,this ADPLL can operate from 72.95MHz to 353.66 MHz, and achieve frequency acquisition in 20 reference clock cycles(best_case),the peak-to-peak jitter <250ps and RMS jitter <143ps when the PLL is locked.With a 1.8V power supply, the proposed DCO has a power consumption range from 0.67mw to 1.54mw, and DCO resolution is better than 1.47ps. The dead zone of the proposed phase frequency detector (PFD) is reduced to 40ps.In addition, aΔ-Σmodulator,programmable divider and SPI interface circuit in RF fractional-N frequency synthesizer were designed. The modulator used MASH 1-1-1 structure .In UMC 0.18μm CMOS process, the equivalent gate count for above circuits is1733, and static timing analysis shows that the highest operation frequency for modulator is 200MHz, and 400MHz for programmable divider.