Design And Implementation Of 1553B Bus Controller IP Core Based On Opcode Control Logic

MIL-STD-1553 B data bus has been widely used in aerospace integrated electronic system.At present,the domestic protocol chips are heavy and bulky,which still needs the tight coupling operation of CPU software.Along with the development of space technology,the weight,volume and power consumption of space missions are demanding.Therefore,it is very important to design a bus controller IP core with autonomous ability,flexible scheduling ability of bus messages and free arrangement of message frames.Based on the deep research of 1553 B bus protocol specification,this paper analyzes the bus controller architecture of core1553 BBC and S?MMIT chips for opcode control logic.Combined with the practical application of aerospace in China,aiming at the disadvantages that 1553 B chips are high level of participation by CPU software,and the less flexibility architecture,A 1553 B Bus Controller IP core with OPCODE control logic is designed and implemented.This message sequence control structure supports highly autonomous BC operation,which greatly reduces the operation burden of CPU software.In this paper,a message sequence control structure is proposed with 11 opcodes and 15 condition codes matching them.By using opcodes,message execution,halt,jump,call,return,start frame timer and other functions can be realized.And the functions of inserting messages,automatically retrying and switching the bus,minor and major frame control can be realized by combining condition codes.In this paper,the top-down design method is applied to divide the logic function modules of bus controller.The design method of each module and the opcode control module are introduced in detail.Based on the Finite State Machine the message sequence control structure with 11 OPCODES is realized.According to the message format specified in 1553 B protocol,the BC protocol analysis module is divided into four sub-modules: RT receive,RT transmit,RT-RT and broadcast.CPU can read and write ram to 1553 B bus controller through CPU interface/ AXI interface.In this paper,Verilog HDL is used to describe hardware of 1553 B bus controller in RTL level,and the combined opcodes testbench files are wrote,include message insertion,automatically retry and bus switching,minor and major frame control.The correctness of the overall module is verified by using Modelsim.It has also passed the simulation verification,which verified the reasonable and correctness of the 1553 B BC IP core based on the OPCODE control logic.