The Design And Implementation Of High Speed 1553B Bus Interface

The characteristics of high-speed, high reliability, real-time in 1553B bus make it wildly used in military and civil fields and developed into an internationally recognized standard data bus. The most critical part in 1553B bus system is bus interface processor, due to the complexity of 1553B bus interface design, at present the chip available on the market are imports from foreign companies, all this make it so expensive, the latest generation products are still embargo against China. The domestic 1553B bus chip are lag behind the world, the low transmission rate of this product make it can not meet the system requirements for usage of high transmission rate. Therefore, research and development of 1553B protocol processor has significant meanings for the construction of national defence and the development of national economy.Based on the deep study of MIL-STD-1553B protocol and GJB289A-97 standard, MIL-HDBK-1553A and GJB/Z209-2002 application handbook, designer and user manual of foreign mainstream chip. Then determine the overall structure, module division, complete the sub-module design and simulation, at last complete board-level debugging on FPGA. This paper primarily introduce the design of Manchester codec, bus controller(BC), remote terminal(RT) and other modules, give the logical diagram, port information and simulation results of each sub-modules.The test results show that the designed 1553B bus interface has lots of merits of high-speed (10Mbps), high reliability, real time, and is compatible with low-speed 1553B products.