1553b Communication Protocol Design And Research, Based On The Soc Technology

MIL-STD-1553B is a kind of avionic bus communication standard, which adoptes centralized control method and the instructions/response model bus. For its biggest characteristic of instantaneity and reliability, it is now widely applied in aviation system and ground-based weapons control system. However, First of all, we must develop bus interface chip.In this paper, after researching the MIL-STD-1553B specifically, and referring to some function structure of foreign chips, we conbine EDA technology and put forward the design scheme of 1553B interface chip based the FPGA. In the research, the function and the code characteristics of the RT,MT,BC and PE(Manchester Encoding) were introduced. Then,The design method of BC was presented in detail and the design method of Rt and MT were also presented briefly.We could select the work mode to make the designed chip working in specified state. In this project we adopted Verilog to program and we designed some standard interface used to link other devices. For example we adopted the Wishbone to communicate and classics plan to join external CPU. SOC was fit for internal IP interconnected. This system clock used the digital phase-locked technology. The deduced precedures of models included the logic diagram chart, algorithm flow chart and function simulation results. EDA tools were used to optimize and synthesize the function module,which realized all terminal function XILINX virtex. It was proved the design could meet three kinds of work about BC/RT/MT by experiments. In addition, the scheme was able to handle much information transmission, and it had strong ability of error check. In the end of the paper, we analyzed the synchronization of information transmission in details and adopted software to improve the time synchronization in basic synchronization mechanism, the algorithm of software could obviously improve the stability and reliability of the system.