Research On Application Of IP Core Interface Technology Based On PLB

With rapid development of the SoPC technology, especially the SoPC design technology based on IP reuse, makes IP interface technology and integrated technology for numerous available IPs on an efficient bus platform which has good expansibility and compatibility high significant.SoPC efficiency depends on the efficiency of bus and interface, low efficiency can cause the ultimate degradation of system performance, also the complicated structure will cost large limited chip system resources.the very complicated PLB bus has been applied to EDK design tools by Xilinx company, and the tools could generate interface module for users, but it still has certain limitation, such as complicated structure, low efficiency, cost larger chip system resources, and so on.At present, this technology is held by international companies, few domestic engaged in these technologies and the research of the development environment. So we must work in this aspect of researching the core technology with independent intellectual property rights.This work aimed at the complex structure, too much resource occupied and low efficiency between the the PLB bus of FPGA. With these limitations, , this work considers how to improve IPIF according to application needs, the main work is presented as following:1. Anglicizing five common PLB bus protocol and complicated PLB bus protocol, also discuss the structure and mechanism of PLB bus interface.2. By researching the bus operation timing and the function and mechanism of IPIF internal module, then implement the PLB bus using VHDL language,with the function of read and write.3. Build a PLB bus interface validation platform,an easy verification strategy was proposed to validate the function of the interface and analysis the results.4.Accompany with the flexible and high-speed features of SoPC , after realizing the basic interface read-write function, we start to explore more efficient method to design the PLB bus interface.