A Design Of Post Placement And Routing Simulation Based On FPGA

A timing analysis method and a post simulation design on FPGA based on LUT are proposed and implemented in this thesis. In the stage of timing analysis, timing node and timing edge, extracted from chip architecture and routing data, are used for building the timing graph. According to the timing graph, the delay values and critical paths of circuits are computed. By calling methods of graphic interface, the delay values are printed and paths between inputs and outputs are highlighted. The problem of lacking delay values of circuit is solved and then the necessary information for simulation after placement and routing are provided. In the stage of Post-Simulation, a tool called P-Sim is designed. During operation, P-Sim get detail information about certain circuit by reading several files, including the LUT value, process those information, then generate a post simulation wave file which will be displayed in the Waveform Analyzer thus timing and logic functions of circuits is verified. Practised with several real circuits, the stability, correctness and fine performance is proved.