Research Of Cell Timing Modeling In FPGA Static Timing Analysis

As a semi-custom circuit in the field of ASIC(Application Specific Integrated Circuit),the appearance of FPGA(Field Programmable Gate Array)not only solves the defect of custom circuit,but also overcomes the disadvantage of the limited number of gates of original programmable devices.STA(Static Timing Analysis)is the most commonly timing analysis method in the circut design used to verify whether timing of the circuit meets timing requirements that designers specify.The cell timing library file need to be read when STA module is running,and this file is usually generated by the Synopsys Liberty format cell timing modeling method.This method is a cell timing modeling method tailored for ASIC,although it can also be used for FPGA,it is not very suitable for FPGA.The Liberty format cell timing modeling method cannot describe timing changes caused by different cell configurations.When the granularity of modeling cell is large,Liberty format cell timing modeling method models the cell and its timing repeatedly.During the construction of timing graphs,the cell timing library generated by the Liberty format cell timing modeling method cannot construct timing graphs according to cell configurations,resulting in the scale of timing graphs being too large.In order to solve problems above,this thesis mainly carried out two aspects of research work:(1)According to programmable features of FPGA,this thesis proposes a cell timing modeling method suitable for FPGA--cell timing modeling method based on FPGA cell configurations.This method can reflect timing changes caused by different cell configurations.Compared with Liberty format cell timing modeling method,this method can avoid modeling timing of cells repeatedly,so the number of timing arcs to be modeled can be reduced,thereby this method can reduce the size of the cell timing library greatly.In addition,since the cell timing library generated by this method includes configuration information of cells,timing graphs can be constructed according to cell configurations.It avoids constructing all timing arcs of the entire cell into the timing graph,but only constructs timing arcs actually used into the timing graph,thereby it can reduce the scale of the timing graph and avoid generating pseudo critical paths.(2)Define the new cell timing information description statement for cell timing modeling method based on FPGA cell configurations.This statement can not only describe the basic timing information,such as type of timing arcs,format of delay values,start point and end point of timing arcs,but also the list of cell configurations corresponding to timing arcs.The cell timing library can be modeled successfully using the new cell timing information description statement.This thesis designs and implements a new cell timing modeling method through above research work.This thesis tests and analyzes a large number of circuit cases to verify the correctness of functions of EDA(Electronics Design Automation)software used in this thesis.This thesis also verifies the feasibility of the new cell timing modeling method,while verifying the correctness of STA module.This thesis also analyzes the performance of STA module,and compares it with the static timing analysis results of the mainstream EDA software ISE to verify the accuracy of STA module.Besides,in the process of realizing STA algorithm,the efficiency of two basic search algorithms of graphs--BFS(Breadth First Search)algorithm and DFS(Depth First Search)algorithm is compared using the data actually measured when traversing timing graphs.It provides theoretical and practical reference for the development of STA module.