Systematic Design Of16bit100MSPS Pipelined A/D Converter

A/D converter, as the interface between the outside and the inside of theelectronic system, needs continuous improvements on integration and complexity withthe increasing requirement on its resolution and speed. Pipelined ADC is a prevailingstructure in the field of high-speed and high-resolution ADC, the systematic design ofwhich is of great importance to its performance.The key parts of Pipelined ADC, such as the front-end Sample and Hold, MDACand comparator, are firstly researched in this paper，and then the relationship betweenthe features of the parts and the features of the ADC, the number of stages and theresolution of the first stage are discussed. The optimization of the systematicarchitecture is also discussed in this paper and a guideline for the determination of thenumber of stages and the resolution of a stage are also brought forward. In the end, asystem configuration with a bidirectional overflow digital correction algorithm isimplemented on a16bit,100MSPS Pipelined ADC, which adopts0.35μm CMOSprocess. A front-end Sample and Hold with a close loop gain of10/9is employed in thePipelined ADC and the pipeline is divided into5stages by the use of capacitor scalingdown.The input range of the16bit,100MSPS Pipelined ADC is1.125V~1.125V. Itchanges to1.25V~1.25V after passing the Front-End Sample and Hold. With the5-4-4-4-3stage resolution distribution, the largest offset voltage of the comparator is±39.0625mV. Based on Matlab, the digital correction algorithm of the systematicarchitecture is simulated in this paper and the results shows that the digital correctionalgorithm is correct and the input signal is converted without missing codes.