Research On Nano-scale SRAM Design For Embedded CPU

As a class of most important cache for the embedded IP application, Static Random Access Memory (SRAM) has become one of the hottest research topics in the digital integrated circuits field. With the development of integrated circuit design goes into nanometer era, the progress of process brings new challenges to the design of embedded SRAM. Focusing on the design of high performance and low power SRAM for the owned 32bits embedded CPU, this thesis starts the following research work:1. To deal with the SRAM stability problem which is affected by the device mismatch induced by the random variations of process parameters in the sub-100nm and beyond, we adopt the Monte-Carlo simulation method to perform statistical failure analysis for SRAM under the read, write and hold modes by invoking SPICE model, which provides a reference guide for the nanometer scale SRAM design.2. Different from the traditional full-custom design approach which is quite time consuming and high cost, a new full-custom and semi-custom combined design method for SRAM is proposed in this thesis. Modules demanding on higher timing and electrical performance are designed by the bottom-up full-custom method, while digital logic modules are designed by the top-down semi-custom method. Besides high efficiency and low cost, this method has good scalability for various capacity of SRAM and is easy to implement in different silicon process.3. We finish a series of on-chip SRAM design for the owned embedded CPU under 90nm process node and develop a design flow which is suitable for the nanometer process. It takes the lead in implementing nanometer custom design for embedded SRAM in domestic, and lays a solid foundation for the SRAM design in 65nm process node and even below.4. With the deep analysis of the system-level timing synchronization problem of embedded memory, this thesis proposes a useful clock skew scheduling based on the particle swarm optimization (PSO) algorithm. This new method adopts the adaptive particle swarm optimization with linearly decreasing inertia weight to search for the optimum useful clock skew without changing circuit structure, and reduces the clock cycle by meanwhile iteratively optimizing the combinational path delays. The experimental results of applying this algorithm to 32-bit embedded CPU show that the system performance is dramatically improved.