Research And Implementation Of Efficient Shared Memory Controller For Multi-Core System

With the Internet services increased explosively, the requirement for network bandwidth is rigorous. The state of art of core network bandwidth has reach OC-768 (40Gbps). The multi-processor architecture becomes main stream in IP-packet processing. It also means processors need more data. Memory access control has become a key factor that impacts the performance of network processor.Based on the netwook processor of XDNP project needs, this paper designs and implements an efficient shared memory controller for multi-core system.On multi-core SoC, it's necessary for multiple commands to queue. The single arbitration algorithm is difficult to meet the system performance requirements and it's hard to implement complicated arbitration algorithm with hardware. Therefore, hierarchical arbitration strategy is adopted by this paper, that is, fixed priority algorithm pays enough consider of priority and improved rotation priority algorithm ensures fairness of the memory access and continuity of read/write commands are guaranteed.More request of access memory, the delay of command waiting,decoding and accessing off-chip memory is longer. In order to solve this problem, this paper adopts commands prefetch technology combined with ping-pang cache structure which can achieve address of read/write instruction transmission in pipeline. The delay of access memory has been hidden effectively.Finally, this paper completes the functional simulation and implementation on the FPGA platform of Xilinx Virtex-IV xc4vlx160. As the result shows, the SRAM controller can complete the SSRAM access for multi-processor. Furthermore, by optimizing the memory bus, the access efficiency improvement is greater than 60% compared with original memory controller. The efficiency of memory access shared by multi-processor cores is improved remarkably.