Design And Optimization Of On-Chip Function-Enhanced Shared SRAM For Heterogeneous Multi-Core Systems

With the development of processor technology,the performance of processors continues to improve.However,the speed of memory performance improvement is far behind the performance of processors.This leads to the emergence of the problem of "Memory Wall".The speed of memory has become a bottleneck restricting the development of processors.This thesis designs a function-enhanced shared cache structure for the target heterogeneous multi-core system.It uses on-chip SRAM as the cache medium and can be used as the system's second-level shared cache or local private cache of the computing cluster.It supports multi-channel parallel memory access.The memory bandwidth of the system is effectively improved,and the performance of the multi-core system is improved.The main work of the thesis is as follows:1.Analyze the memory access characteristics and data organization form of the target heterogeneous multi-core system,and design a function-enhanced shared cache structure that can switch part of the cache resources between the second-level shared cache and the local private cache.Designed and optimized the cache structure,designed the data interaction strategy among the cache,the system and the main memory,and formulated its switching strategy between different modes.2.According to the design plan,the hardware design of the shared cache structure is carried out.It divides the modules in detail,and introduces the structure of each module,the function performed and the working principle.It mainly includes the relevant module design of task management,the relevant module design of the cache area,the reconfigurable design of the execution mode switching,the data channel design and the data channel arbiter design.3.Integrate the designed function-enhanced shared cache structure into the target heterogeneous multi-core system,load different types of tasks,and test the effect of the function-enhanced shared cache structure on system performance.The results of the experiments show that,compared with the original storage cluster,the average performance of the matrix transposition task without computing time is improved by 0.8%.For tasks that have computing time,the average performance of tasks that do not involve mode switching is increased by 35.6%;the average performance of tasks that require mode switching is increased by 8.6%;for a comprehensive task that is executed alternately by multiple tasks,the average performance is increased by 16.5%.In summary,the function-enhanced shared cache structure designed in this thesis can effectively improve system performance and achieve the expected design goals.