Research On Key Technology Of Multi - Core Processor

Multi-core processors are gradually replacing the traditional single core processors, and have been widely used in embedded applications. Multi-core processors can achieve high performance by reasonable task scheduling, partitioning and parallelizing. But for many applications, the task parallelism is limited, so the performance cannot grow linearly with the number of cores deployed. In order to further improve performance, adding dedicated or reconfigurable hardware accelerators to the processors is an efficient solution. In this thesis, we propose a heterogeneous execution array as the hardware accelerator to achieve both efficiency and flexibility.On the other hand, the memory organization and data management is also challenging for multi-core processors. With the growing amount of core numbers, supporting distributed shared memory is becoming a general trend. A multi-core architecture based on distributed shared memory is explored and compared to centralized memory.The main work and innovation of this thesis include:(1) Double-layer NoC to connect the execution arrayThe heterogeneous execution array proposed by this thesis is interconnected via a NoC which is an effective fusion of the packet-switched network and circuit-switched network. Flexible configuration is realized through packet-switched network while efficient data transmission based on circuit-switched network is also supported. This double layer network interconnection makes the heterogeneous execution array scale well and be highly shared among the multi-core processors.(2) Shadow register file mapping interfacesBased on the characteristics of NoC and multi-core processors, the communication interfaces of the heterogeneous and multi-core processors are mapped in the shadow register file. Processors can access the execution array through normal read/write instructions of register file which simplifies operations between the execution array and processor. The configurable extension of register file provides high-speed communication interfaces and improves data locality at the same time.(3) Embedded application specific units design In this thesis, execution units of application specific accelerators are designed for the multimedia and communication applications to improve their performance, generic units such as adders and multipliers are also included. Those execution units provide configurability, efficiency and flexibility.(4) Chip implementation and applicationsAfter finishing the RTL design and verification, a24-core processor with proposed heterogeneous execution array is implemented in TSMC65nm LP CMOS process flow with ICC ILM hierarchical layout design. The chip contains two kinds of clusters, cluster I with heterogeneous execution array and cluster II without. The chip size is4mm*4.4mm, in which a single area of heterogeneous execution array is965um*742um. The max operating clock frequency under1.2V is850MHz.(5) Distributed shared memory systemA multi-core architecture based on distributed shared memory is explored and evaluated via an H.264decoder application. In this thesis, a multi-core H.264decoder on an FPGA is implemented and a comparison of distributed memory with centralized memory system is presented.