Research And Design Of Multi-core Shared SDRAM Controller Of Network Processor

With the development of computer architecture, circuit design and IC manufacture technology, the performance of CPU grows rapidly. Memory is one of the crucial devices in the digital system. It is important to design an effective memory system for the best capability of system. While its time sequence and access mechanisms are very complex, it is necessary to design an excellent SDRAM controller to improve the efficiency of accessing.The technologies of multi-core shared SDRAM controller of network processor such as basic operation, arbitration, interface, data transfer and timing are explored in this dissertation. In multi-core multi-thread network processor, the SDRAM controller is shared by StrongARM, process engine (PE) and fast bus interface (FBI), which can wake up sleeping thread and support arbitration for access requests from different functional modules. In order to access SDRAM fairly, effectively and timely, a hierarchical priority arbitration mechanism is adopted, including the fixed priority and TDMA (Time Division Multiplexed Access). Besides, a dynamic arbitration algorithm mechanism is added, which hides SDRAM precharge delay to improve the efficiency of SDRAM access. The data transport protocol is developed and verified to make sure that the data transfer without errors between SDRAM memory and StrongARM, PE, FBI. The open page and odd even bank interleaving optimization are introduced to improve the data transfer rate by reducing the precharge and active delay. The memory access latency can be reduced by 10% with the open page optimization. The results show that odd even bank interleaving optimization reduces execution time by up to 48%.Based on the research of main feature inside SDRAM controller, several function modules of the controller are designed and implemented. The RTL design of the controller is completed with hardware description language verilogHDL. The design has been simulated and synthesized in the ISE empolder entironment, and has been verified in hardware environment via Xilinx FPGA.