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Modeling Shared Cache Memory Accesses Of Multi-core Processors

Posted on:2018-09-27Degree:MasterType:Thesis
Country:ChinaCandidate:L F ZhangFull Text:PDF
GTID:2348330542469226Subject:Integrated circuit engineering
Abstract/Summary:PDF Full Text Request
With the rapidly development of electronics and information technology,multi-core processors have been widely used in the embedded devices.Shared cache,one of the most important part of processor's performance of multi-core processors,has aroused increasing interests in academia and industry.The understanding of the shared cache performance mechanism,not only provides design space exploration to the hardware designers,but also helps the software designers to optimize the memory access pattern of their software.This thesis aims to develop a rapid and accurate model to predict the memory access performance of shared cache with prefetch mechanism.The work of this thesis contains two parts:firstly,adding logical code to make the cycle-accurate simulator,Gem5,to extract the memory access reuse distance distributions of shared cache by each core individually,and then calculating the reuse distances of interleaved access stream presented to the shared cache.Secondly,After verifying and analyzing the modeling method that based on expected stack distance from studies,this thesis establishes a neural network model for the shared cache with prefetch mechanism.Due to the impact of prefetch mechanism to the stack distance,the prediction precision of expected stack distance model decresed siginificantly.Therefore,this theis proposes an ANN(Artificial neural network)model to predict the memory access behavior of shared cache in multi-core processors.The ANN model uses the reuse distance distribution of shared cache as input,and hit numbers of shared cache as output.This theis chooses Mobybench2.0 benchmark to assess the predict accuracy of the ANN model.From the reference to the experiment results,compared to the results from Gem5 cycle accurate simulation,the average relative error of the ANN model is less than 20%,the minmum error of the model is 13.7%,and the ANN model can bring over 53.2%average time reduction.Meanwhile,the predict precision of ANN model is 20%-30%higher than the model which based on the expected stack distance.The experiment results shows that the precision of the ANN model meet the design index,and match the design requirement.
Keywords/Search Tags:mutil-core processor on chip(CMP), shared cache modeling, stack distance distribution of memory access, prefetch, ANNs
PDF Full Text Request
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