Research On Key Technologies Of Scalable 64-core Processor-- Network-on-chip、memory Hierarchy And LTE Implementation

In recent years, embedded applications such as multi-media, communication, information security and cloud computing become increasingly important and effect our daily life. The continuously updating protocols for these applications lead to the requirement of flexible and reconfigurable designing and implementation for those products. This thesis has designed a multi-core platform for these specific applications. In order to adapt closely to both data flowing and computing feature of each application, this multi-core platform adopts the topology of globally mesh-locally star for network-on-chip, high performance distributed shared memory design within the cluster, and transaction shared memory between clusters, supporting asynchronous clock domains switching. The main work and innovation of this thesis are as follows:(1) Novel topology for network-on-chipThe development of 64-core processor aims at great balance between area, performance and power for specific applications. A novel globally mesh-locally star topology is proposed in this thesis, to reduce the chip area comparing to the traditional 2-D mesh topology while not effecting network transmitting efficiency.(2) High performance shared memory design within the clusterThe 64-core processor adopts a distributed shared memory scheme within the cluster based on strict consistency. On this basis, a direct-memory-access communication method is proposed, which achieves the auto transmitting of data through network on chip. With rational backend floorplan and physical design, each memory accessing operation is performed within one clock cycle, which means the memory hierarchy of the whole chip is efficient.(3) Transaction shared memory design between clustersFor streaming applications such as communication and multimedia, it is usually not enough to use cores within one cluster. Besides network-on-chip, programmers prefer a convenient and efficient transmitting method for large data block between clusters. Thus, this thesis proposes an extended distributed memory hierarchy with synchronous function and supporting transaction sharing between asynchronous clock domains. It has good program portability and high efficiency for synchronization and transmission.(4) Chip implementation and application (LTE) implementationAfter the frontend design and verification, this thesis further implements backend physical design. A 64-core processor including 8 clusters, each of which consists of 8 MIPS cores and some accelerators, is designed and implemented using TSMC 65nm GP process. The area of this chip is 4663.4*4790um2, and the clock frequency is 1GHz, at which the power is 21.4mW for each core node. Further, this thesis implements LTE downlink receiving channel carrier frequency synchronization and FFT mapping solution on this multi-core processor, and achieves the target performance.