Design And Optimization On Multi-core Shared Memory Controller Based On Network Processor

The research and design of Multi-core shared SDRAM controller of Network processoris explored in this thesis. In order to complete the design of multi-core shared memorycontroller, the on-chip interface for queue structure, the priority-based arbitration formemory access instruction, push-pull engine for the data exchange between multi-coreprocessor and memory, interface of memory controller are designed and analyzed in thethesis. And the asynchronous memory access between the multi-core shared memorycontroller and the multi-core network processor is mainly discussed.The dataforwarding between the RFIFO and TFIFO units in the on-chip packet buffer and thememory can be achieved directly through DMA channel.Considering the long memory access latency brought about by SDRAM memory, thearchitecture of the multi-core shared memory is improved and optimized. Combinedwith the requirements of memory to act as forwarding and packet buffer, the circuits forpre-taking instructions are added and the interface of memory controller is alsoimproved to support the dynamic optimization on SDRAM memory. The controllersystem can take the same bank and row optimization or bank interleaving dynamicallyaccording to the relationship of two consecutive instructions, which can maximize thenumber of the instructions for optimization.Al last, the function of multi-core shared memory controller designed with RTL code isverified on the XDNP verification platform. And the results show that the functionalmodules of memory controller can finish the task successfully and the whole controllercan assistant the network processor to complete the access to off-chip SDRAM memory.The performance analysis shows that the dynamic optimization based on instructionspre-take controller can offer a better performance than the controller that only takes astatic optimization. The more instructions are executed the more space for performancecan be obtained. When the number of instructions is greater than35, the improvedperformance of system can reach45%and become stable at this number due to thelimitation of packet program for micro-engine.