Fractional Frequency Synthesizer Design

Frequency synthesizer is a complex mixed analog-digital radio system that contains high frequency voltage controlled oscillator and the prescaler, low-frequency charge pump, filter, and a large number of digital logic circuits. Frequency synthesizer in the design process will need in the design of many parameters of a compromise, such as phase noise, settling time, power consumption, area, high-frequency input and output matching. In this paper, proposed a general high-frequency purity, high-resolution, low phase noise, multi-band output of the fractional-N frequency synthesizer system base SMIC 0.18um analog/RF technology,that can compatible with the widely used virous types of wireless communication standards and satellite positioning systems. Firstly using Verilog-A language for the fractional frequency synthesizer behavioral modeling and simulation, and to determine the charge pump current, voltage controlled oscillator gain, loop filter capacitors & resistors, etc; Second, implementation the frequency synthesizer circuit in each cell, and its prescaler based on current mode logic (CML) technology to achieve the high-frequency work, programmable divider using the general digital circuit technology; fractional divider associated with three oder Sigma-Delta modulator (SDM_MSAH₁-1-1) to suppress fractinal supri; voltage controlled oscillator uses digital tuning technology for broadband work and multi-frequency output, the frequency tuning range is 900MHz-2250MHz, phase noise is less than 70dBc/Hz @ 10kHz. Finally, finishing the frequency synthesizer system simulation and verification, the locking time is less than 30us, to achieve a rapid lock.