Design methodology for an analogue voltage multiplier macro cel

The development of an Analogue Voltage Multiplier (AVM) macro cell using a Complementary Metal-Oxide-Semiconductor (CMOS) fabrication process is described in this thesis. A CMOS macro cell implementation presents several problems that are not encountered with single AVM chips fabricated on bipolar processes. The main objectives of this work are to identify factors that limit the performance of a CMOS AVM macro cell and to develop techniques to overcome these problems. Investigation of several types of AVM architectures led to the development of two AVMs, a CMOS AVM which uses only CMOS Field-Effect Transistors (FETs) and a pseudo-BiCMOS AVM which uses bipolar transistors in addition. The bipolar transistor is fabricated using only standard CMOS implant layers. Detailed testing of the integrated AVMs highlights a number of problems concerned with scale-factor stability. The average scale-factors of the CMOS AVMs and the pseudo-BiCMOS AVMs were 36% smaller and 12.5% larger than the designed values respectively. The average non-linearity of the pseudo-BiCMOS AVM is 4.3 times smaller than that of the CMOS AVM but the input offset voltages of the pseudo-BiCMOS AVM were an order of magnitude higher. Using knowledge gained from the initial designs a third AVM circuit design was undertaken using only CMOS FETs. The scale-factor of this AVM is stabilised using a novel circuit configuration technique. HSPICE Monte Carlo simulations and a bread board circuit show that the scale-factor of this circuit may be stabilised with a tolerance of 3% on the designed value. Enhancement of the performance of the multiplier circuits developed are considered using auto-zero techniques to overcome the problems of offset voltage.