The Research Of Digital Filter Implementation Technology Based On FPGA

The implementation of digital signal processing system is facing many challenges along with the increasing applications of digital signal processing technology. Rate, design scale, power and exploitation period are four primary problems among them. Therefore, many implementation methods are put forward, and the implementation technology based on FPGA is one of them.This dissertation focuses on the implementation technology of digital filters based on FPGA, with the background of the implementations of digital signal processing system. It contains two main parts:In the first part, the design method and design flow of FPGA are summarized, taking the example of Xilinx's FPGA, and on a basis of it, a new design manner for fast development called System Generator is introduced, which provides the designer of digital signal processing system with a top-down resolvent of FPGA。In the second part, the implementation of digital filters in FPGA is studied systematacially. Three implementation methods of FIR filter, which are fit for FPGA, are studied first. They are direct structure, transpose structure and distribute arithmetic. Second, the multiplier optimizing technology—CSD coding, coefficient analyze for direct structure and reduced adder graph for transpose structure, are discussed. Also the optimizing effect is presented with the examples. Third, two implementation methods of multioperand addition—Binary Tree and Wallace Tree, are introduced. And then on a basis of Wallace Tree, a structure of one-bit multioperand addition fitting for FPGA is presented, which can reduce the resource utiiance in implementing FIR filter whose sample data and coefficient are both one-bit. Finally, the merit, demerit and applicability of the three implementation methods in FPGA are presented and a band-pass filter is designed and implemented.The results of this dissertation has been applied to the BD-I navigation and positioning receivers.