Design Of ?R Digital Filter Based On FPGA

With the development of digital signal processing (DSP) technology, the history of digital filters dates back to mid-1970s. Over the past 30 years, the design of digital filters has become an enabling technology. Digital filters, in fields such as communications, control, defense, biomedicine and radar, has become the sole choice, replacing analog filters. Digital filters are digital devices that can change the property of signals in digital ways. Their own properties can be presented with amplitude and phase response of frequency, both being functions of frequency. Except for changing signals in a specified way, digital filters themselves must comform to other requirements, such as speed, complexity, cost and power comsumption. While in some high performance conditions, microprocessors are usually replaced by FPGA or ASIC or DSP with parallel computing structures to explore the potential of the digital filters. Generally in the category of digital filters, most of them can be classified into 2 categories:finite impulse response filters and infinite impulse response filters.This paper is organized through the research of ?R digital filters in MATLAB environment and implementation and test on FPGA development board. The paper starts with the research fundamentals of digital ?R filters, first thoroughly summarizing various kinds of digital filters and their corresponding characteristics in the history of digital ?R filters. Theoretical fundamentals of ?R filter design, including choice of prototypes, implementation architectures, design method and finite word-length effects, are then introduced. The structure used in this paper is determined. Secondly, low pass filter with cascaded elliptical structure is designed based on SOS (second order section) with the FDAtool in MATLAB. The coefficients of the designed filter is then discretized according to finite word-length effect theory. Then the filter is dynamically simulated using Simulink. The simulation process showed that the impulse response of the designed filter is generally stable, and performance of frequency filtering is met.Finally, RTL coding is performed according to the previously designed IIR digital filter. In the Simulink and ModelSim co-simulation environment, functional verification of the filter is performed. Verilog HDL code is compiled in Quartus ? and downloaded the code to FPGA development board for testing. Quantative test is done using SignalTap ?, complete test of ?R filter is further accomplished with hardware platform. Analysis showed that, the passband stop frequency of ?R digital filter is 496.6kHz, starting frequency of stopband is 522.9kHz, attenuation of stopband is 57.7dB and the ripple of passband is smaller than 1.5dB. The designed IIR digital filter basically meet the design specifications, and the performance of filtering is qualified.